The Cyrix 6x86 is a sixth-generation, 32-bit 80x86-compatible microprocessor designed by Cyrix and manufactured by IBM and SGS-Thomson. The 6x86 combines aspects of both RISC and CISC. It has a superscalar, superpipelined core, and performs register renaming, speculative execution, out-of-order completion , and data dependency removal . It has a 16-kilobyte primary cache and is socket-compatible with the Intel Pentium P54C .  It was also unique in that it was the only x86 design to incorporate a 256-byte Level 0 scratchpad cache.  It has six performance levels: PR 90+, PR 120+, PR 133+, PR 150+, PR 166+ and PR 200+. These performance levels do not map to the clock speed of the chip itself (for example, a PR 133+ ran at 110MHz, a PR 166+ ran at 133MHz, etc). The 6x86L was later released by Cyrix to address heat issues; the L standing for low-power.

The architecture of the 6x86 is more advanced than that of the Intel Pentium, incorporating some of the features of the Intel Pentium Pro. At a given clock rate it executes most code more quickly than a Pentium would. However, its FPU is considerably less efficient than Intel's.

Note that the 6x86 and 6x86L weren't completely compatible with the Intel Pentium instruction set. It is for this reason that by default the chip identified itself as a 486 and disabled the CPUID instruction. CPUID support could be enabled by first enabling extended CCR registers then setting bit 7 in CCR4.

A later release of the 6x86, the 6x86MX, added MMX compatibility and quadrupled the primary cache size to 64 kilobytes.