Science Fair Project Encyclopedia
This article is about the term counter used in electronics and computing. For other meanings of counter, see counter (disambiguation)
In general, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred often in relationship to a clock. In practice, there are two types of counters:
- up counters which increase (increment ) in value
- down counters which decrease (decrement ) in value
Counters in electronics
- Asynchronous (ripple) counters
- Synchronous counters
- Johnson counters
- Decade counters
Each is useful for different applications. Usually, counter circuits are digital in nature, and count in binary, or sometimes binary coded decimal. Many types of counter circuit are available as digital building blocks, for example a number of chips in the 4000 series implement different counters.
The simplest counter circuit is a single D-type flip flop, with its D (data) input fed from its own inverted output. This circuit can store one bit, and hence can count from zero to one before it overflows. By cascading a series of D-type flip flops, a ripple counter is formed, which can count to 2n-1 where n is the number of bits (flip flop stages) in the counter. Ripple counters suffer from unstable outputs as the overflows "ripple" from stage to stage, but they do find frequent application as dividers for clock signals, where the instantaneous count is unimportant, but the division ratio overall is. (To clarify this, a 1-bit counter is exactly equivalent to a divide by two circuit - the output frequency is exactly half that of the input when fed with a regular train of clock pulses).
Where a stable count value is important across several bits, which is the case in most counter systems, synchronous counters are used. These also use flip-flops, either the D-type or the more complex J-K type, but here, each stage is clocked simultaneously by a common clock signal. Logic gates between each stage of the circuit control data flow from stage to stage so that the desired count behaviour is realised. Synchronous counters can be designed to count up or down, or both according to a direction input, and may be presettable via a set of parallel "jam" inputs. Most types of hardware-based counter are of this type.
Decade counters are a kind of counter that counts in tens rather than having a binary representation. Each output will go high in turn, starting over after ten outputs have occurred. This type of circuit finds applications in multiplexers and demultiplexers, or wherever a scanning type of behaviour is useful. Similar counters with different numbers of outputs are also common.
A Johnson counter is a special case of shift register, where the output from the last stage is inverted and fed back as input to the first stage. A pattern of bits equal in length to the shift register thus circulates indefinitely. These counters are sometimes called "walking ring" counters, and find specialist applications, including those similar to the decade counter, digital to analogue conversion, etc.
See also: Frequency counter
Counters in computer science
In computability theory, a counter is considered a type of memory. A counter stores a single natural number (initially zero) and can be arbitrarily-many digits long. A counter is usually considered in conjunction with a finite state machine (FSM), which can perform the following operations on the counter:
- Check whether the counter is zero
- Increment the counter by one
- Decrement the counter by one (if it's already zero, this leaves it unchanged)
The following machines are listed in order of power, with each one being strictly more powerful than the one below it:
- Deterministic or Non-deterministic FSM plus two counters
- Non-deterministic FSM plus one stack
- Non-deterministic FSM plus one counter
- Deterministic FSM plus one counter
- Deterministic or Non-deterministic FSM
For the first and last, it doesn't matter whether the FSM is deterministic or non-deterministic (see determinism). They have equivalent power. The first two and the last one are levels of the Chomsky hierarchy.
The first machine, an FSM plus two counters, is equivalent in power to a Turing machine. This equivalence can be shown in three steps. First, a Turing machine can be simulated by two stacks. Then, a stack can be simulated by two counters. Finally, four counters can be simulated by two counters.
Step 1: A Turing machine can be simulated by two stacks.
A Turing machine consists of an FSM and an infinite tape, initially filled with zeros, upon which the machine can write ones and zeros. At any time, the read/write head of the machine points to one cell on the tape. This tape can be conceptually cut in half at that point. Each half of the tape can be treated as a stack, where the top is the cell nearest the read/write head, and the bottom is some distance away from the head, with all zeros on the tape beyond the bottom. Accordingly, a Turing machine can be simulated by an FSM plus two stacks. Moving the head left or right is equivalent to popping a bit from one stack and pushing it onto the other. Writing is equivalent to changing the bit before pushing it.
Step 2: A stack can be simulated by two counters.
A stack containing zeros and ones can be simulated by two counters, when the bits on the stack are thought of as representing a binary number, with the top being the least significant bit. Pushing a zero onto the stack is equivalent to doubling the number. Pushing a one is equivalent to doubling and adding 1. Popping is equivalent to dividing by 2, where the remainder is the bit that was popped. Two counters can simulate this stack, in which one of the counters holds a number whose binary representation represents the bits on the stack, and the other counter is used as a scratchpad. To double the number in the first counter, the FSM can initialize the second counter to zero, then repeatedly decrement the first counter once and increment the second counter twice. This continues until the first counter reaches zero. At that point, the second counter will hold the doubled number. Halving is performed by decrementing one counter twice and increment the other once, and repeating until the first counter reaches zero. The remainder can be determined by whether it reached zero after an even or an odd number of tries.
Step 3: Four counters can be simulated by two counters.
As before, one of the counters is used as scratchpad. The other, real counter holds an integer whose prime factorization is 2a3b5c7d. The exponents a, b, c, and d can be thought of as four virtual counters that are being simulated. If the real counter is set to zero then incremented once, that is equivalent to setting all the virtual counters to zero. If the real counter is doubled, that is equivalent to incrementing a, and if it's halved, that's equivalent to decrementing a. By a similar procedure, it can be multiplied or divided by 3, which is equivalent to incrementing or decrementing b. Similarly, c and d can be incremented or decremented. To check if a virtual counter such as c is equal to zero, just divide the real counter by 5, see what the remainder is, then multiply by 5 and add back the remainder. That leaves the real counter unchanged. The remainder will have been nonzero if and only if c was zero.
As a result, an FSM with two counters can simulate four counters, which are in turn simulating two stacks, which are simulating a Turing machine. Therefore, an FSM plus two counters is at least as powerful as a Turing machine. A Turing machine can easily simulate an FSM with two counters, therefore the two machines have equivalent power.
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