Science Fair Project Encyclopedia
- This article is about the electronic component. For other meanings, see flip-flop (disambiguation).
In electronics and computing, the flip-flop or bistable multivibrator is a pulsed digital circuit capable of serving as a one-bit memory. A flip-flop typically includes zero, one, or two input signals; a clock signal; and an output signal, though many commercial flip-flops additionally provide the complement of the output signal. Some flip-flops also include a clear input signal, which resets the current output. (In actuality, flip-flops are implemented as integrated circuit chips that also require power and ground connections.) Pulsing, or strobing, the clock causes the flip-flop to either change or retain its output signal, based upon the values of the input signals and the characteristic equation of the flip-flop. (Strobing the clock is a simplified view: any change of output state actually coincides with either the leading edge or the trailing edge of the clock pulse. The manufacturer's specification, or data sheet, annotates the precise semantics.)
Four types of flip-flops find common applicability in clocked sequential systems : these are called the T ("toggle") flip-flop, the S-R ("set-reset") flip-flop, the J-K flip-flop, and the D ("delay") flip-flop. The behavior of the flip-flop is described by what is termed the characteristic equation, which derives the "next" (i.e., after the next clock pulse) output, Qnext, in terms of the input signal(s) and/or the current output, Q.
Types of flip-flops
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is described by the characteristic equation:
and the truth table:
The "set/reset" flip-flop sets (i.e., changes its output to logic 1, or retains it if it's already 1) if both the S ("set") input is 1 and the R ("reset") input is 0 when the clock is strobed. The flip-flop resets (i.e., changes its output to logic 0, or retains it if it's already 0) if both the R ("reset") input is 1 and the S ("set") input is 0 when the clock is strobed. If both S and R are 0 when the clock is strobed, the output does not change. If, however, both S and R are 1 when the clock is stobed, no particular behavior is guaranteed. This is often written in the form of a "truth table":
or more explicitly, showing the pre-clock value of Q as if it were another input:
X means "don't care", or the output will be the same regardless of which state the X is in.
Left: A circuit symbol for a SR-type flip-flop, where > is the clock input, S is the set input, R is the reset input, Q is the stored data output, and Q' is the inverse of Q.
It is the responsibility of the circuit designer to ensure that the S = R = 1 condition does not arise. Given this externally imposed condition, one typically avoids writing a characteristic equation for the S-R flip-flop. Various "master-slave" interconnections of S-R flip-flops are possible to achieve particular behaviors.
The J-K flip-flop augments the behavior of the S-R flip-flop by interpreting the S = R = 1 condition as a "flip" command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K turns the J-K flip-flop into a T flip-flop.
Left: A circuit symbol for a J-K flip-flop, where > is the clock input, J and K are data inputs, Q is the stored data output, and Q' is the inverse of Q.
The characteristic equation of the J-K flip-flop is:
and the truth table is:
The D ("delay") flip-flop takes one input, which it conveys to the output when the clock is strobed. Regardless of the current value of the output, it will assume a value 1 if D = 1 when the flip-flop is strobed or a value 0 if D = 0 when the flip-flop is strobed. This flip-flop can be interpreted as a primitive delay line or zero-order hold , since the data is posted at the output one clock cycle after it arrives at the input.
Left: A circuit symbol for a D-type flip-flop, where > is the clock input, D is the data input and Q is the stored data output.
The characteristic equation of the D flip-flop is:
The truth table is:
The flip-flop can be used to store one bit, or binary digit, of data. The data contained in several such flip-flops may represent the state of a sequencer, the value of a counter, an ASCII character in a computer's memory or any other piece of information.
The "T" flip-flop is useful for counting. Repeated signals to the clock input will cause the flip-flop to change state once per high-to-low transition of the clock input, if its T input is "1". The output from one flip-flop can be fed to the clock input of a second and so on. The final output of the circuit, considered as the array of outputs of all the individual flip-flops, is a count, in binary, of the number of cycles of the first clock input, up to a maximum of 2n-1, where n is the number of flip-flops used.
One of the problems with such a counter (called a ripple counter) is that the output is briefly invalid as the changes ripple through the logic. There are two solutions to this problem. The first is to sample the output only when it is known to be valid. The second, more widely used, is to use a different type of circuit called a synchronous counter. This uses more complex logic to ensure that the outputs of the counter all change at the same, predictable time.
Frequency division: a chain of "T" flip-flops as described above will also function to divide an input in frequency by 2n, where n is the number of flip-flops used between the input and the output.
Timing and Metastability
Clocked flip-flops are prone to a problem called metastability, which happens when a data or control input is changing at the instant of the clock pulse. The result is that the output may behave unpredictably, taking many times longer than normal to settle to its correct state, or even oscillating several times before settling. In a computer system this can cause corruption of data or a program crash.
In many cases, metastability in flip-flops can be avoided by ensuring that the data and control inputs are held constant for specified periods before and after the clock pulse, called the setup time (tsu) and the hold time (th) respectively. These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few hundred nanoseconds for modern devices.
Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one feeds the data input of the next, and all devices share a common clock. With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero.
So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a matter of circuit design. When the transitions in the clock and the data are close together in time, the flip-flop is forced to decide which event happened first. However fast we make the device, there is always the possibility that the input events will be so close together that it cannot detect which one happened first. It is therefore logically impossible to build a perfectly metastable-proof flip-flop.
Another important timing value for a flip-flop is the clock-to-output delay (common symbol in data sheets: tCO) or propagation delay (tP), which is the time the flip-flop takes to change its output after the clock edge. The time for a high-to-low transition (tPHL) is sometimes different from the time for a low-to-high transition (tPLH).
When connecting flip-flops in a chain, it is important to ensure that the tCO of the first flip-flop is longer than the hold time (tH) of the second flip-flop, otherwise the second flip-flop will not receive the data reliably. The relationship between tCO and tH is normally guaranteed if both flip-flops are of the same type.
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