In electronics, a hardware description language or HDL is any language from a class of computer languages for formal description of electronic circuits. It can describe circuit's operation, its design, and tests to verify its operation by means of simulation.

An HDL is a standard text-based expression of the temporal behaviour and/or (spatial) circuit structure of an electronic system. In contrast to a software programming language, an HDL's syntax and semantics include explicit notations for expressing time and concurrency which are the primary attributes of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as netlist languages.

Frequently (and incorrectly), the term programming is used to be synonymous with writing a hardware description. This often arises because of the goal that HDLs be executable specifications of some piece of hardware. A simulation program, designed to implement the underlying semantics of the language statements and the progression of time, provides the hardware designer with the ability to model a piece of hardware before it is created physically. This execution capability makes it seem like the language is used to program something. Simulators capabable of supporting discrete event (digital), and continuous time (analog) modeling exist and HDL's targeted for each are available.

It is certainly possible to represent hardware semantics using traditional programming languages such as C++ (and augmented with extensive and unwieldy class libraries.) However, the C++ language does not include any capability for expressing time explicitly and consequently is not a proper hardware description language.

Using the proper subset of virtually any (hardware description or software programming) language a software program called a synthesizer can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives to implement the specified behaviour. This typically (as of 2004) requires the synthesizer to ignore the expression of any timing constructs in the text. The ability to have a synthesizable subset of the language does not itself make a hardware description language.

Designing a system in HDL is generally much harder and more time consuming than writing a program that would do the same thing using a programming language like C. Consequently, there has been much work done on automatic conversion of C code into HDL, but this has not reached a high level of commercial success as of 2004.

Design using HDL

HDLs are used to design two kinds of systems. First, they are used to design a dedicated integrated circuit, such as a processor or other kind of digital logic chip. In this case, HDL specifies a model for the expected behaviour of a circuit before that circuit is designed and built. The end result is a silicon chip that would be manufactured in a fab.

The second use involves programming the programmable logic devices, such as the FPGAs. The HDL code is fed into a logic compiler, and the output is uploaded into the device. The unique property of this process, and of the programmable logic in general, is that it is possible to alter the code many times, compile it, and upload into the same device for testing.

Simulating and debugging HDL code

Essential to HDL design is the ability to simulate HDL programs. An HDL program may be tested in hardware, such as by uploading it into a programmable logic device or even by producing a chip based on its specification. However, this is generally a very time-consuming and costly process, and generally the bulk of testing and debugging is done using a program called simulator. The simulator maintains a resettable "clock", similar to the real clock of a digital device, and allows the designer to print out the values of various registers over time in order to debug the code.

HDL and programming languages

An HDL is analogous to a software programming language, but with subtle differences. Both types of language are processed by a compiler (usually called a synthesizer in the HDL case). An HDL compiler often works in several stages, first producing a logic description file in a proprietary format, then converting that to a logic description file in the industry-standard EDIF format, then converting that to a JEDEC-format file. The JEDEC file contains instructions to a PLD programmer for building logic.

On the other hand, a software compiler generates instructions to a microprocessor for moving data. The difference between HDLs and software languages is becoming less distinct as reconfigurable systems are beginning (in 2002) to combine features of both.

HDLs used for digital circuit design include:

• Verilog HDL
• VHDL
• ABEL HDL ("Advanced Boolean Expression Language", a proprietary language developed by the Data I/O Corporation and now owned by Lattice Semiconductor)
• AHDL (Altera HDL, a proprietary language from Altera)
• CUPL (a proprietary language from Logical Devices, Inc. )
• JHDL
• Hardware Description Languages in the Open Directory

There are attempts to create HDL for analog circuit design.

The current trend is to move away from proprietary HDLs and towards the two leading standards, VHDL and Verilog HDL.

External links

There also attempts to create high-level description languages, i.e. high-level languages for low-level descriptions. Examples of this new work are:

• Confluence (a functional programming language for reactive system design, released under GNU GPL).
• Lava (Xilinx use Haskell for HDL)