Science Fair Project Encyclopedia
Originally Merced had been intended as a new high performance server architecture, to replace Intel's Xeon line of processors. As a proprietary architecture (not derived from x86), AMD would not be able to clone it. Over time, there was even an aspiration it might transition to high end desktops.
The first version, code named Merced, shipped in June 2001. Manufactured in a 180 nm process, it was offered at speeds of 733 and 800MHz, with a choice of 2MB or 4MB off-die L3 cache. Prices ranged from US$1200 to over US$4000. However, performance was disappointing. In IA-64 mode, it performed only slightly better than an equivalently clocked x86 design, and when running x86 code, performance was extremely poor, about 1/8th that of an similarly clocked x86 processor.
The main (though by no means only) structural design flaw with the Itanium, was the high latency of its level three cache. Intel's engineers had evidently been hoping that the amount of bandwidth available would offset this, but the latency was so high that it actually slowed the cache to the point, where it was not significantly faster than the main memory interface. With the faster first and second-level caches set relatively small (32KB and 96KB respectively), this further increased the load on the main system bus. Compounding the performance impact of the lack of available cache bandwidth, was the fact IA-64 code has a larger footprint than x86 code. So the amount of instructions that could be contained in the cache, was in fact even smaller than the sizes alone would suggest.
All of which might have been mitigated, had Itanium been designed around a fast processor bus. However, at a mere 266MHz it was only equal to consumer Athlons of the period, and a full 33% slower than first generation Pentium 4 . Again, this was worse than it would appear, due to the fact that Itaniums were designed to be used in systems with several processors. Itanium clock speeds were also disappointing, relative to the GHz speeds being delivered by the Athlon architecture of the period.
Overall, it is generally believed that the technical specifications indicate an original 1998-99 target launch date. But the repeated and lengthy project delays, effectively meant the processor was out of date before it had even begun shipping. Hence, the Itanium came up badly lacking compared to what was available when it was actually launched.
It was succeeded by the Itanium 2.
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