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Technically, the chip put the architecture back on track and obtained leadership performance in many benchmarks. Impressively for an in-order processor, some two and a half years after its release the Itanium 2 core remains the most efficient processor according to the SPECint2000/GHz and SPECfp2000/GHz metrics. It also has the highest outright SPECfp2000 result.
All Itanium 2 processors to date share a common cache hierarchy. They have 16 kB of Level 1 instruction cache and 16 kB of Level 1 data cache. The L2 cache is unified (both instruction and data) and is 256 kB. The Level 3 cache is also unified and varies in size from 1.5 MB to 9 MB. In an interesting design choice, the L2 cache contains sufficient logic to handle semaphore operations without disturbing the main ALU. Montecito, however, features a split L2 cache, adding a dedicated 1MB L2 cache for instructions and thereby effectively growing the original 256 kB L2 cache, which becomes a dedicated data cache.
The Itanium 2 bus is occasionally referred to as the Scalability Port, but much more frequently as the McKinley bus. It is a 200 MHz, 128-bit wide, double pumped bus capable of 6.4 GB/s — more than three times the bandwidth of the Merced bus. In 2004, Intel released processors with a 266 MHz bus, increasing bandwidth to 8.5 GB/s. Rumour has it that 2005 will see a 333 MHz bus.
The future of the Itanium family apparently lies in multi-core chips, as the available information about coming generations like Montecito/Montvale and Tukwila (those are internal code names; the final products will most likely also bear the Itanium brand) shows.
McKinley was the first version of Itanium 2, manufactured in an 180 nm process. It was released at speeds of 900 MHz and 1 GHz, with cache sizes of 1.5 MB and 3 MB. It added hardware support for the branchlong instruction of the IA-64 instruction set. IA-32 performance, while improved, was still much slower than that of current x86 processors; McKinley's x86 performance was similar to that of a Pentium II at 2/3 the clock speed.
Madison was initially introduced on June 30, 2003. It was initially available in three versions: 1.3 GHz with 3 MB of cache, 1.4 GHz with 4 MB of cache and 1.5 GHz with 6 MB of cache. Manufactured in an 130 nm process, it had a die size of 374 mm². Its power envelope remained unchanged from McKinley at 130 watts. On September 8, 2003, a 1.4 GHz version with 1.5 MB of cache was released. A 1.6 GHz version with 6 MB of cache and a 1.4 GHz version with 3 MB of cache were launched on April 13, 2004. November 8, 2004 saw the release of a 1.6 GHz version with 9 MB cache.
Hondo was announced as the HP mx2 dual-processor module on February 18, 2003 and started shipping in early 2004. It consists of two Madison cores with 32 MB of L4 cache and fits in the same space as a normal Itanium 2 CPU. It is only available from HP. Currently the cores run at 1.1 GHz with 4 MB L3 cache each.
Deerfield was released on September 8, 2003. With 1.5 MB of cache, running at 1 GHz, this was the first low voltage Itanium processor. Its 62 watt power envelope made it more suited for blade and 1U servers.
The Fanwood core debuted on November 8, 2004. Versions include a 1.6 GHz edition with 3 MB of L3 cache with either 200 MHz or 266 MHz FSB and a low voltage 1.3 GHz version with 3 MB L3 cache at 200 MHz.
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