OpenCores is a loose collection of people who are interested in developing digital hardware through electronic design automation, with a similar ethos to the free software movement. Currently the emphasis is on digital modules called 'cores', commonly known as IP-components . The components are used for creating both custom integrated circuits (ASICs) and FPGAs.

The cores are implemented in the hardware description languages Verilog or VHDL, which may be synthesized to either silicon or grid arrays.

The components produced by the OpenCores initative use several different software licenses, but the most common is GNU LGPL, which states that any modifications to a component must be shared with the community, while you can still use it together with proprietary components.

The project aims at using a common non-proprietary system bus named Wishbone, and most components are nowadays adapted to this bus.

Among the components created by OpenCores contributors are:

• OpenRISC - a highly configurable RISC central processing unit
• A Zilog Z80 clone
• USB 2.0 controller
• Ethernet controller, 100/10 Mbit
• Encryption units, for example DES

See also

• Open hardware

External links

• OpenCores web site : http://www.opencores.org/