Science Fair Project Encyclopedia
The PDP-11 was a 16-bit minicomputer sold by Digital Equipment Corp. in the 1970s and 1980s. The PDP-11 was a successor to DEC's PDP-8 computer in the PDP series of computers. It had several uniquely innovative features, and was easier to program because it had a highly-orthogonal instruction set which allowed a programmer to separately memorize all of the operations and the methods of accessing operands. They could then predict that any access method (or "addressing mode") would work with any operation; they did not have to learn a list of exceptions or special cases in which an operation had a special or restricted set of addressing modes. In some logical sense, the set of addressing modes provided one "basis", and the set of operations provided another. Each two-operand instruction was separated into two six-bit operand identifiers (each consisting of a three-bit register number, and a three-bit addressing mode) and a four-bit op-code; single-operand instructions had one six-bit operand identifier, and a ten-bit op-code. All op-codes operated with any operand identifier address mode (or combination of them, for the two-operand instructions). Of the 8 registers (numbered 0 through 7), 7 were general-purpose and could be used for most purposes, although register 6 was specially recognized by the hardware as the stack pointer for some instructions; register 7 was the program counter. This latter innovation, together with some of the addressing modes, provided constants, absolute addresses, and relative (position independent) addressing.
In the most radical departure from other, earlier computers, the PDP-11 had no dedicated bus for input/output; it had only a memory bus. All input and output devices were mapped to addresses in memory, so in addition, no special I/O instructions were needed. The interrupt system was intentionally designed to be as simple as possible, while assuring that no event in an interrupt sequence could be missed. A device would request an interrupt by asserting a common input into one of four priority lines; the processor would respond over an interrupt daisy chain grant line, one for each priority level. (A daisy chain is a sequence of logic gates arranged in series to order events. Generally the first logic gate has first access to the grant. The daisy chain order established the order of the devices at that priority level.) In the case of the PDP-11 design, this meant that the interrupt grant order was determined by how close the physical hardware was to the CPU on the bus. When the CPU responded, the device would place its vector address on the bus; this was the address of a 4-byte block of memory. The CPU would then load the status register and program counter from the vector table; the new contents of the status register would generally temporarily disable interrupts. The address in the program counter would be the starting address of the code to run for the interrupt. The interrupt code would then service the device, and in the process, write to the interrupting device to re-enable the interrupt signal. Finally, a special RTI (return from interrupt) instruction would return the CPU to where it was before the interrupt (which might have been in a lower-priority interrupt). Note that this process prevents loss of interrupts; at every stage, if the interrupt is not serviced, it remains in place, to be sensed on the next cycle. If a sequence is erroneously started, the CPU would time out, generating a special spurious interrupt; the spurious interrupt would warn users of bad hardware.
Finally, the PDP-11 was designed to be produced in a factory by semiskilled labor. All of the dimensions of its pieces were relatively noncritical. All parts of the computer chassis were constructed from injection-molded plastic, or bent steel rod (lighter than sheet metal). It used a push-bonded backplane. That is, the printed circuit board plugged into a backplane connector. The backplane connector had terminals that could be connected by pushing wires into them. The terminal would cut the insulation around the wire and bite into the wire to form a gas-tight (i.e. corrosion-proof, therefore reliable) connection. The connector blocks were very similar to telephone connection blocks. The case was injection-molded plastic that snapped over the steel-rod chassis.
The LSI-11 was the first PDP-11 model produced using large-scale integration; the entire CPU was contained on 4 LSI chips. It used a bus which was a close variant of the Unibus called the Q-Bus; it differed from the Unibus primarily in that addresses and data were multiplexed onto a shared set of wires, as opposed to having separate sets of wires, as in the Unibus. It also differed slightly in how it addressed I/O devices and it eventually allowed a 22-bit physical address (whereas the Unibus only allowed an 18-bit physical address) and block-mode operations (which the Unibus did not support).
The CPU's microcode includes a debugger that directly communicated to a standard RS-232 terminal. This was innovative because the microcode is the part of the irreducible guts of the computer, a critical part of the control unit. If it doesn't work, there is no computer. The debugger provided a way to examine the computer's registers, memory and input and output devices. Thus, if the CPU worked at all, it was possible to examine and correct the computer's internal state. The built-in debugger avoided the expense and inconvenience of a front panel with an array of switches and lights, which was then the typical way to enter digital data into a near-dead computer.
The microcode also included a generic bootstrap, to which all DEC disk drives were compatible.
These two innovations meant that most of the time, the computer just worked. If it did not boot from its big disk, it would boot from its floppy. If the hardware worked at all, it talked to you through a terminal in a familiar way.
The Decline of the PDP-11
Although the basic architecture was extremely good, and the PDP-11 line was continually updated to use newer technologies, it finally died off for one principal reason: the 16-bit virtual address space was simply too small. When large VLSI memory chips became very cheap, the PDP-11 was just not capable of using large amounts of memory easily.
DEC's own successor to the PDP-11, the VAX (for "Virtual Address Extension (to the PDP-11)") addressed all of these issues, but was aimed at the high-end market.
As engineers migrated to architectures which supported a larger address space, 32-bit computing began to be supported on microprocessor chips such as the Motorola 68000 and Intel 386 families; eventually the economics of large-scale production of those chips made them so cheap there was no cost advantage for the PDP-11.
The following information is found in DEC's PDP-11 Processor Handbook (see Gordon Bell's 1969 edition).
General register addressing modes
(R is a general register, 0 to 7; (R) is the contents of that register.)
- 0. Register - the value is to or from a register: OPR R ; R contains operand
- 1. Register deferred - register is used as a memory address to read or write: OPR (R) ; R contains address
- 2. Autoincrement: OPR (R)+ ; R contains address, then increment (R)
- 3. Autoincrement deferred: OPR @(R)+ ; R contains address of address, then increment (R) by 2
- 4. Autodecrement: OPR -(R) ; Decrement (R), then R contains address
- 5. Autodecrement deferred: OPR @-(R) ; Decrement (R) by 2, then R contains address of address
- 6. Index: OPR X(R) ; (R)+X is address, second word of instruction
- 7. Index deferred: OPR @X(R) ; (R)+X is address (second word) of address
Program Counter addressing modes
The program counter (PC) can also be used as a general purpose register, providing the following effectively additional addressing modes, using the mechanisms of the addressing modes above:
- 2. Immediate: OPR #N ; Operand is contained in the instruction
- 3. Absolute: OPR @#A ; Absolute address is contained in the instruction
- 6. Relative: OPR A ; PC+4+X is address. PC+4 is updated PC
- 7. Relative deferred: OPR @A ; PC+4+X is address of address. PC+4 is updated PC
- Single Operand instructions - one part of the word specifies the operation, referred to as "op code", the second part provides information for locating the operand.
- CLR (clear), COM (ones complement), INC (increment), DEC (decrement), NEG (twos complement negate), TST (test), ASR (arithmetic shift right), ASL (arithmetic shift left), ROR (rotate right), ROL (rotate left), SWAB (swap bytes), ADC (add carry), SBC (subtract carry), SXT (sign extend).
- Double Operand instructions - the first part of the word specifies the operation to be performed, the remaining two parts provide information for locating the operands.
- MOV (move), ADD, SUB (subtract), ASH (shift arithmetically), ASHC (arithmetic shift combined), BIT (bit test), BIC (bit clear), BIS (bit set), XOR (exclusive OR).
- Program Control instructions - the first part of the word specifies the operation to be performed, the second part indicates where the action is to take place in the program.
- BR (branch unconditionally), BNE (branch if not zero), BEQ (branch if zero), BPL (branch if plus), BMI (branch if minus), BVC (branch if overflow clear), BVS (branch if overflow set), BCC (branch if carry clear), BCS (branch if carry set).
- BLE (branch if <= 0), BGE (branch if >= 0), BLT (branch if < 0), BGT (branch if > 0) (signed compares).
- BLO (branch if lower), BHI (branch if higher), BLOS (branch if lower or same), BHIS (branch if higher or same) (unsigned compares).
- SOB (subtract one from register and branch if not = 0).
- Jump & Subroutine instructions
- JMP (jump), JSR (jump to subroutine), RTS (return from subroutine).
- EMT (emulator trap), TRAP, BPT (breakpoint trap), IOT (input/output trap), RTI & RTT (return from interrupt).
- Miscellaneous instructions
- HALT, WAIT (wait for interrupt), RESET (reset UNIBUS), MTPD (move to previous data space), MTPI (move to previous instruction space), MFPD (move from previous data space), MFPI (move from previous instruction space), MTPS (move to processor status word), MFPS (move byte from processor status word).
- Condition Code operations
- CLC, CLV, CLZ, CLN, CCC (clear relevant condition code), SEC, SEV, SEZ, SEN, SCC (set relevant condition code).
- The four condition codes in the processor status word (PSW) are
- N indicating a negative value
- Z indicating a zero condition
- V indicating an overflow condition, and
- C indicating a carry condition.
- "Floating Instruction Set" (FIS), option for 11/35/40 and 11/03
- FADD, FSUB, FMUL, FDIV only for single precision operating on stack addressed by register operand
- "Floating Point Unit" (FPU), option for 11/45 and most subsequent models
- full floating point operations on single or double precision operands, selected by single/double bit in Floating Point Status Register
- single precision floating point data format precessor of IEEE 754 format: sign bit, 8bit exponent, 23bit mantissa with hidden bit 24
- Commercial Instruction Set (CIS), option for 11/23/24, one version of 11/74
Assembly Language Programming Example
.TITLE HELLO WORLD .MCALL .TTYOUT,.EXIT HELLO:: MOV #MSG,R1 ;STARTING ADDRESS OF STRING 1$: MOVB (R1)+,R0 ;FETCH NEXT CHARACTER BEQ DONE ;IF ZERO, EXIT LOOP .TTYOUT ;OTHERWISE PRINT IT BR 1$ ;REPEAT LOOP DONE: .EXIT MSG: .ASCIZ /HELLO, WORLD!/ .END HELLO
(Exercise for the reader: how can the above code be improved to avoid one of the branch instructions in the inner loop?)
If this file is HELLO.MAC, the RT-11 commands to assemble, link and run (with console output shown) are as follows:
.MACRO HELLO ERRORS DETECTED: 0
.R HELLO HELLO, WORLD! .
(The RT-11 command prompt is ".")
For a more complicated example of MACRO-11 code, two examples chosen at random are Kevin Murrell's KPUN.MAC, or Farba Research's JULIAN routine. More extensive libraries of PDP-11 code can be found in the Metalab freeware and Trailing Edge archives.
You can try out the above for yourself on a PDP-11 emulator. Bob Supnik's outstanding simh emulates the PDP-11 and a variety of other architectures, and includes software kits for native operating systems (including RT-11).
The PDP-11 processors tended to fall into several natural groups depending on the original design upon which they are based and which I/O bus they used. Within each group, most models were offered in two versions, one intended for OEMs and one intended for end-users.
The following models used the Unibus as their principal bus:
- PDP-11 (later renamed the PDP-11/20) and PDP-11/15 -- The original, direct execution processor.
- PDP-11/35 and 11/40 -- A microprogrammed successor to the /20.
- PDP-11/45, 11/50, and 11/55 -- A much faster microprogrammed processor that could use semiconductor memory as well as or in addition to core memory.
- PDP-11/70 -- The 11/45 architecture expanded to allow 4MB of physical memory segregated onto a private memory bus, 2KB of cache memory, and much faster I/O devices connected via the Massbus .
- PDP-11/05 and 11/10 -- A cost-reduced successor to the 11/20.
- PDP-11/34 and 11/04 -- Cost-reduced follow-on products to the 11/35 and 11/05. The PDP-11/09 and 11/39 model names were documented internally to DEC but never produced for sale.
- PDP-11/44 -- An extension of the 11/34 that included the cache memory and floating point units as a standard feature. This machine also included a sophisticated serial console and support for 4MB of physical memory segregated onto its own private bus.
- PDP-11/60 -- A PDP-11 with user-writable microcontrol store.
The following models used the Q-Bus as their principal bus:
- PDP-11/03 (also known as the LSI-11/03) -- The first LSI PDP-11, this system used a chipset from Western Digital.
- PDP-11/73 -- The third generation LSI PDP, this system used the "Jaws-11" chip set.
- PDP-11/53 -- downsized 11/73
Models that were available for either bus
- PDP-11/23 and 11/24 -- The second, much faster LSI PDP-11, it used the "Fonz-11" chipset. This system supported 4MB of physical memory and the Commercial Instruction Set.
- The 11/23+ supported 4 MB, while the 11/23 supported less. It was possible to hack the 11/23 hardware to make it an 11/23+.
- PDP-11/83 and 11/84 -- Another J-11 implementation.
Models that were planned but never introduced
- PDP-11/27 -- A Jaws-11 implementation that would have used the VAXBI Bus as its principal I/O bus.
- PDP-11/74 -- A PDP-11/70 that was extended to contain multiprocessing features. Up to four processors could be interconnected, although the physical cable management became unwieldy. Another variation on the 11/74 contained both the multiprocessing features and the Commercial Instruction Set.
- PDP-11/68 -- A follow-on to the PDP-11/60 that would have supported 4MB of physical memory.
Special purpose versions
- H-11 -- Heathkit version of the LSI-11/03, packaged within a VT52-compatible terminal
- MINC-11 -- Laboratory system based on 11/03 or 11/23.
- C.mmp -- Multiprocessor system from Carnegie_Mellon_University.
The PDP-11 was sufficiently popular that several unauthorized clones were produced behind the Iron curtain. At least some of these were pin-compatible with DEC's PDP-11s and could share peripherals and system software. These include:
- SM-4, SM-1420, SM-1600 , Electronics BK-0010, DVK, UKNC (in the Soviet Union)
- SM-4, SM-1420, IZOT-1016 and peripherials (in Bulgaria).
- SM-1420 (in East Germany)
- Mera (in Poland)
- SM-4 (in Hungary)
- Independent (in Romania)
Several operating systems were available for the PDP-11
From third parties:
- The PDP-11 FAQ
- Another PDP-11 fansite
- PDP-11s behind the Iron Curtain
- Russian PDP-11 clones (cyrillic web).
- Museum of the USSR Computers history
- Gordon Bell and Bill Strecker's 1975 paper, What We Learned From the PDP-11
- Further papers and links on Gordon Bell's site.
- A PDP-11 back-end (code generation templates) for the retargetable ANSI Little_C_compiler
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