Science Fair Project Encyclopedia
Property Specification Language
Property Specification Language is a language standardized by Accellera for specifying properties or assertions about hardware designs. It comes in two flavors, one for VHDL and one for Verilog.
More information is available at
Last updated: 08-30-2005 09:33:46
10-26-2009 08:16:03
The contents of this article is licensed from www.wikipedia.org under the GNU Free Documentation License. Click here to see the transparent copy and copyright details
The contents of this article is licensed from www.wikipedia.org under the GNU Free Documentation License. Click here to see the transparent copy and copyright details


