Science Fair Project Encyclopedia
Streaming SIMD Extensions
SSE (Streaming SIMD Extensions) is a SIMD instruction set designed by Intel, and introduced in their Pentium III series processors as a reply to AMD's 3DNow!, which had debuted a year or so earlier. It was originally known as KNI for Katmai New Instructions (Katmai was the code name for the Pentium III). During the Katmai project Intel was looking to distinguish it from their earlier product line, particularly their flagship Pentium II. AMD eventually added support for SSE instructions in its Athlon XP processor.
Intel was generally disappointed with their first IA-32 SIMD effort, MMX. MMX had two main problems: it re-used existing floating point registers making the CPU unable to work on both floating point and SIMD data at the same time, and it worked on only integers.
SSE adds eight new 128-bit registers known as XMM0 through XMM7. Each register packs together four 32-bit single-precision floating point numbers.
Because these 128-bit registers are additional program state that the operating system must preserve across task switches, they are disabled by default until the operating system explicitly enables them. This means that the OS must know how to use the FXSAVE and FXRSTR instructions, which is the extended pair of instructions which can save all x86, MMX, 3DNow!, and SSE register states all at once. This support was quickly added to all major IA-32 operating systems.
Because SSE adds floating point support, it sees much more use than MMX now that the graphics cards all handle integer calculations internally. Integer SIMD operations may still be performed with the eight 64-bit MMX registers. The MMX registers are "aliased" on top of the eight FPU registers. Note: starting with the SSE2 version, even integers can be handled through the SSE XMM registers, so the MMX instruction set is now redundant.
On the Pentium 3, however, SSE is implemented using the same circuitry as the FPU, meaning that, once again, the CPU cannot issue both FPU and SSE instructions at the same time for pipelining. The separate registers do allow SIMD and scalar floating point operations to be mixed without the performance hit from explicit MMX/floating point mode switching.
Intel's Pentium 4 implements SSE2, an extension to the basic SSE instruction set. The major features of SSE2 are support for double-precision (64-bit) floating point numbers and support for integer data types in the 128-bit vector registers introduced with SSE, allowing the programmer to avoid the MMX/FPU registers. SSE2 has itself been extended by SSE3.
The contents of this article is licensed from www.wikipedia.org under the GNU Free Documentation License. Click here to see the transparent copy and copyright details