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Turbo code

Turbo codes are a class of recently-developed high-performance error correction codes finding use in deep-space satellite communications and other applications where designers seek to achieve maximal information transfer over a limited-bandwidth communication link in the presence of data-corrupting noise. Of all practical error correction methods known to date, turbo codes come closest to approaching the Shannon limit, the theoretical limit of maximum information transfer rate over a noisy channel.

The method was introduced by Berrou, Glavieux, and Thitimajshima in their 1993 paper: "Near Shannon Limit error-correcting coding and decoding: Turbo-codes" published in the Proceedings of IEEE International Communications Conference [1]. Turbo code refinements and implementation are an area of active research at a number of universities.

Turbo codes make it possible to increase available bandwidth without increasing the power of a transmission, or they can be used to decrease the amount of power used to transmit at a certain data rate. Its main drawback is a relatively high latency, which makes it unsuitable for some applications. For satellite use, this is not of great concern, since the transmission distance itself introduces latency due to the limited speed of light. Turbo codes are used extensively in 3G mobile telephony standards.

Prior to Turbo codes, the best known technique combined a Reed-Solomon error correction block code with a Viterbi algorithm convolutional code.

Contents

1 External links

How turbo codes work

There are two related features of turbo codes that make them different from the more traditional error-correcting codes of the 20th century:

  • The key insight is the realization that instead of producing a stream of binary digits from the signal it receives, the front-end of the decoder can be designed to produce a likelihood measure for each bit.
  • The nitty-gritty of turbo codes is the design of the decoder (and the coder) so that it can exploit this additional information.

The encoder

Then encoder sends three sub-blocks of bits. The first sub-block is the m-bit block of payload data. The second sub-block is n/2 parity bits for the payload data, computed using a convolutional code. The third sub-block is n/2 parity bits for a known permutation of the payload data, again computed using a convolutional code. That is, two redundant but different sub-blocks of parity bits for the payload are sent. The complete block has m+n bits of data with a code rate of m/n.

The decoder

The decoder front-end produces an integer for each bit in the data stream. This integer is a measure of how likely it is that the bit is a 0 or 1. The integer could be drawn from the range [-127, 127], where:

  • -127 means "certainly 0"
  • -100 means "very likely 0"
  • 0 means "it could be either 0 or 1"
  • 100 means "very likely 1"
  • 127 means "certainly 1"
  • etc

This introduces a probabilistic aspect to the data-stream from the front end, but it conveys more information about each bit than just 0 or 1.

For example, for each bit, the front end of a traditional wireless-receiver has to decide if an internal analog voltage is above or below a given threshold voltage level. For a turbo-code decoder, the front end would provide a integer measure of how far the internal voltage is from the given threshold.

To decode the m+n-bit block of data, the decoder front-end creates a block of likelihood measures, with one likelihood measure for each bit in the data stream. There are two parallel decoders, one for each of the n/2-bit parity sub-blocks. Both decoders use the sub-block of m likelihoods for the payload data. The decoder working on the second parity sub-block knows the permutation that the coder used for this sub-block.

Solving hypothises to find bits

The nitty gritty of turbo codes is how they use the likelihood data to reconcile differences between the two decoders. Each of the two convolutional decoders generates a hypothesis (with derived likelihoods) for the pattern of m bits in the payload sub-block. The hypothesis bit-patterns are compared, and if they differ, the decoders exchange the derived likelihoods they have for each bit in the hypotheses. Each decoder incorporates the derived likelihood estimates from the other decoder to generate a new hypothesis for the bits in the payload. Then they compare these new hypotheses. This iterative process continues until the two decoders come up with the same hypothesis for the m-bit pattern of the payload, typically in 4 to 10 cycles.

External links

12-03-2008 10:22:39
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