Science Fair Project Encyclopedia
The bus was an advanced, configuration-free synchronous bus used on DEC's later VAX computers. Like the Unibus and Q-Bus before it, it used memory-mapped I/O but allowed 32 bits for its address and data paths. The VAXBI was a multiplexed bus with fully-distributed arbitration and geographic addressing.
All of the logic required to implement a VAXBI interface was contained within a single LSI integrated circuit and the physical layout and printed wiring board layup for compliant cards was tightly specified, right down tothe location of the dual amber status LEDs that were required. The portion of the card that was reserved for the bus interface was referred to as "the VAXBI corner". VAXBI licensees were given the appropriate engineering drawings to allow them to exactly replicate a compliant card.
VAXBI cards mounted into backplanes using a ZIF (Zero insertion force) connector; depending on the backplane design, cards could be loaded from the top or the front side of the backplane. No cable connections were permitted on the cards; all connetions were made via three uncommitted rows of backplane connectors. Similarly, no configuration jumpers were permitted on the cards; all setup was done by jumpers connected inserted onthe backplane connectors or via software configurtion.
Originally conceived by its engineers to be an open standards bus, it was forced to be a tightly-licensed bus by Digital's marketing and management, and was not nearly as successful as had originally been hoped-for.
It was used on the following VAX processors:
- Scorpio (the VAX 82xx/83xx)
- Nautilus (the VAX 85xx/87xx/88xx)
- Aquarius and Aridus (the VAX 9000)
A PDP-11 implementation (the PDP-11/27) was also envisioned but never advanced beyond the concept stage.
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