Science Fair Project Encyclopedia
The architecture is called x86 because the earliest processors in this family were identified only by numbers ending in the sequence "86": the 8086, the 80186, the 80286, the 386, and the 486. Because one cannot trademark numbers, Intel and most of its competitors began to use trademarkable names such as Pentium for subsequent generations of processors, but the earlier naming scheme has stuck as a term for the entire family. Intel now refers to x86 as IA-32, an abbreviation for Intel Architecture, 32-bit.
The x86 architecture first appeared inside the Intel 8086 CPU in 1978; the 8086 was a development of the 8008 processor (which itself followed the 4004). It was adopted (in the simpler 8088 version) three years later as the standard CPU of the IBM PC. The ubiquity of the PC platform has resulted in the x86 becoming one of the most successful CPU architectures ever.
Other companies also manufacture or have manufactured CPUs conforming to the x86 architecture: examples include Cyrix (now owned by VIA Technologies), NEC Corporation, IBM, IDT, and Transmeta. The most successful of the clone manufacturers has been AMD, whose Athlon series is a close second to the Pentium series for popularity.
The 8086 was a 16-bit processor; the architecture remained 16-bit until 1985, when the 32-bit 80386 was developed. Subsequent processors represented refinements of the 32-bit architecture, introducing various extensions, until in 2003 AMD developed a 64-bit extension to the architecture in the form of the AMD64 standard, introduced with the Opteron processor family, which was also adopted a few years later (under a different name) in a new generation of Intel Pentiums.
Note that Intel also introduced a separate 64-bit architecture used in its Itanium processors which it calls IA-64. IA-64 is a completely new system that bears no resemblance whatsoever to the x86 architecture; it should not be confused with IA-32, which is essentially synonymous with x86.
The x86 architecture is essentially CISC with variable instruction length. Word sized memory access is allowed to unaligned memory addresses. Words are stored in the little-endian order. Backwards compatibility has always been a driving force behind the development of the x86 architecture (the design decisions this has required are often criticised, particularly by proponents of competing processors, who are frustrated by the continued success of an architecture widely perceived as quantifiably inferior). Modern x86 processors translate the x86 instruction set to more RISC-like micro-instructions upon which modern micro-architectural techniques can be applied.
Note that the names for instructions and registers (mnemonics) that appear in this brief review are the ones specified in Intel documentation and used by Intel (and compatible, eg. Microsoft's MASM, Borland's TASM, CAD-UL's as386, etc.) assemblers. An instruction that is specified in the Intel syntax by mov al, 30h is equivalent to AT&T-syntax movb $0x30, %al, and both translate to the two bytes of machine code B0 30 (hexadecimal). You can see that there is no trace left in this code of either "mov" or "al", which are the original Intel mnemonics. If we wanted, we could write an assembler that would produce the same machine code from the command "move immediate byte hexadecimally encoded 30 into low half of the first register". However, the convention is to stick to Intel's original mnemonics.
Intel 8086 and 8088 had 14 16-bit registers. Four of them (AX, BX, CX, DX) were general purpose (although each had also an additional purpose; for example only CX can be used as a counter with the loop instruction). Each could be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). In addition to them, there are 4 segment registers (CS, DS, SS and ES). They are used to form a memory address. There are 2 pointer registers (SP which points to the bottom of the stack, and BP which can be used to point at some other place in the stack or the memory). There are two index registers (SI and DI) which can be used to point inside an array. Finally, there are the flag register (containing flags such as carry, overflow, zero and so on), and the instruction pointer (IP) which points at the current instruction.
In real mode, memory access is segmented. This is done by shifting the segment address left by 4 bits and adding an offset in order to receive a final 20-bit address. Thus the total address space in real mode is 220 bytes, or 1 MB, quite an impressive figure for 1978. There are two addressing modes: near and far. In far mode, both the segment and the offset are specified. In near mode, only the offset is specified, and the segment is taken from the appropriate register. For data the register is DS, for code is CS, and for stack it is SS. For example, if DS is A000h and SI is 5677h, DS:SI will point at the absolute address DS × 16 + SI = A5677h.
In this scheme, two different segment/offset pairs can point at a single absolute location. Thus, if DS is A111h and SI is 4567h, DS:SI will point at the same A5677h as above. In addition to duplicity, this scheme also makes it impossible to have more than 4 segments at once. Moreover, CS, DS and SS are vital for the correct functioning of the program, so that only ES can be used to point somewhere else. This scheme, which was intended as a compatibility measure with the Intel 8085 has caused no end of grief to programmers.
In addition to the above-said, the 8086 also had 64K of 8-bit (or alternatively 32K of 16-bit) I/O space, and a 64K (one segment) stack in memory supported by hardware. Only words (2 bytes) can be pushed to the stack. The stack grows downwards, its bottom being pointed by SS:SP. There are 256 interrupts, which can be created by both hardware and software. The interrupts can cascade, using the stack to store the return address.
16-bit protected mode
The Intel 80286 could support 8086 real mode 16-bit software without any changes, however it also supported another mode of work called the protected mode, which expanded addressable physical memory to 16MB and addressable virtual memory to 1GB. This was done by using the segment registers only for storing an index to a segment table. There were two such tables, the GDT and the LDT, holding each up to 8192 segment descriptors, each segment giving access to up to 64 KB of memory. The segment table provided a 24-bit base address, which could then be added to the desired offset to create an absolute address. In addition, each segment could be given one of four privilege levels (called the rings).
Although the introductions were an improvement, they were not widely used because a protected mode operating system could not run existing real mode software as processes. Such capability only appeared with the virtual 8086 mode of the subsequent 80386 processor.
In the meantime, operating systems like OS/2 tried to ping-pong the processor between protected and real modes. This was both slow and unsafe, as in real mode a program could easily crash the computer. OS/2 also defined restrictive programming rules which allowed a Family API or bound program to run either in real mode or in protected mode. This was however about running programs originally designed for protected mode, not vice-versa. By design, protected mode programs did not suppose that there is a relation between selector values and physical addresses. It is sometimes mistakenly believed that problems with running real mode code in 16-bit protected mode resulted from IBM having chosen to use Intel reserved interrupts for BIOS calls. It is actually related to such programs using arbitrary selector values and performing "segment arithmetic" described above on them.
This problem also appeared with Windows 3.0. Optimally, this release wanted to run programs in 16-bit protected mode, while previously they were running in real mode. Theoretically, if a Windows 1.x or 2.x program was written "properly" and avoided segment arithmetic it would run indifferently in both real and protected modes. Windows programs generally avoided segment arithmetic because Windows implemented a software virtual memory scheme and moved program code and data in memory when programs were not running, so manipulating absolute addresses was dangerous; programs were supposed to only keep handles to memory blocks when not running, and such handles were quite similar to protected-mode selectors already. Starting an old program while Windows 3.0 was running in protected mode triggered a warning dialog, suggesting to either run Windows in real mode (it could presumably still use expanded memory, possibly emulated with EMM386 on 80386 machines, so it was not limited to 640KB) or to obtain an updated version from the vendor. Well-behaved programs could be "blessed" using a special tool to avoid this dialog. It was not possible to have some GUI programs running in 16-bit protected mode and other GUI programs running in real mode, probably because this would require having two separate environments and (on 80286) would be subject to the previously mentioned ping-ponging of the processor between modes. In version 3.1 real mode disappeared.
32-bit protected mode
The Intel 80386 introduced, perhaps, the greatest leap so far in the x86 architecture. With the notable exception of the Intel 80386SX , which was 32-bit yet only had 24-bit addressing (and a 16-bit data bus), it was all 32-bit - all the registers, instructions, I/O space and memory. To work with the latter, it used a 32-bit extension of Protected Mode. As it was in the 286, segment registers were used to index inside a segment table that described the division of memory. Unlike the 286, however, inside each segment one could use 32-bit offsets, which allowed every application to access up to 4GB without segmentation and even more if segmentation was used. In addition, 32-bit protected mode supported paging, a mechanism which made it possible to use virtual memory.
No new general-purpose registers were added. All 16-bit registers except the segment ones were expanded to 32 bits. Intel represented this by adding "E" to the register mnemonics (thus the expanded AX became EAX, SI became ESI and so on). Since there was a greater number of registers, instructions and operands, the machine code format was expanded as well. In order to provide backwards compatibility, the segments which contain executable code can be marked as containing either 16 or 32 bit instructions. In addition, special prefixes can be used to include 32-bit instructions in a 16-bit segment and vice versa.
Paging and segmented memory access were both required in order to support a modern multitasking operating system. Linux, 386BSD, Windows NT and Windows 95 were all initially developed for the 386, because it was the first CPU that made it possible to reliably support the separation of programs' memory space (each into its own address space) and the preemption of them in the case of necessity (using rings). The basic architecture of the 386 became the basis of all further development in the x86 series.
The Intel 80387 math co-processor was integrated into the next CPU in the series, the Intel 80486. The new FPU could be used to make floating point calculations, important for scientific calculation and graphic design.
MMX and beyond
1996 saw the appearance of the MMX (Matrix Math Extensions, though sometimes incorrectly referred to as Multi-Media Extensions) technology by Intel. While the new technology has been advertised widely and vaguely, its essence is very simple: MMX defined 8 64-bit SIMD registers overlayed onto the FPU stack to the Intel Pentium CPU design. Unfortunately, these instructions were not easily mappable to the code generated by ordinary C compilers, and Microsoft, the dominant compiler vendor, was slow to support them even as intrinsics. MMX also is limited to integer operations. These technical shortcomings caused MMX to have little impact in its early existence. Nowadays, MMX is typically used for some 2D video applications.
In 1997 AMD introduced the 3DNow! which were SIMD floating point instruction enhancements to MMX (targeting the same MMX registers). While this did not solve the compiler difficulties, the introduction of this technology coincided with the rise of 3D entertainment applications in the PC space. 3D video game developers and 3D graphics hardware vendors used 3DNow! to help enhance their performance on AMD's K6 and Athlon series of processors.
In 1999 Intel introduced the SSE instruction set which added 8 new 128 bit registers (not overlayed with other registers). These instructions were analogous to AMD's 3DNow! in that they primarily added floating point SIMD.
In 2001 Intel introduced the SSE2 instruction set which added 1) a complete complement of integers instructions (analogous to MMX) to the original SSE registers and 2) 64-bit SIMD floating point instructions to the original SSE registers. The first addition made MMX almost obsolete, and the second allowed the instructions to be realistically targeted by conventional compilers.
Introduced in 2004 along with the Prescott revision of the Pentium 4 processor, SSE3 added specific memory and thread-handling instructions to boost the performance of Intel's HyperThreading technology.
As of 2002, the x86 architecture began to reach some design limits due to the 32-bit character length. This makes it more difficult to handle massive information stores larger than 4 GB, such as those found in databases or video editing.
Intel had originally decided to completely drop x86 compatibility with the 64-bit generation, by introducing a new architecture called IA-64. IA-64 technology is the basis for its Itanium line of processors. IA-64 is not software compatible with x86 software natively; it uses various forms of emulation to run x86 software.
AMD took the initiative of extending out the 32-bit x86, aka IA-32 to 64-bit. It came up with an architecture, called AMD64 (it was called x86-64 until being rebranded), and the first products based on this technology were the Opteron and Athlon 64 family of processors. Due to the success of the AMD64 line of processors, Intel adopted the AMD64 instruction set and added some new extensions of their own, rebranding it the EM64T architecture (apparently not wishing to acknowledge that the instruction set came from its main rival).
This was the first time that a major upgrade of the x86 architecture was initiated and originated by a manufacturer other than Intel. Perhaps more importantly, it was the first time that Intel actually accepted technology of this nature from an outside source.
x86 virtualization is difficult because the architecture does not meet the Popek and Goldberg virtualization requirements. Nevertheless, there are several commercial x86 virtualization products, such as VMware and Microsoft Virtual PC. Intel and AMD have both announced that future x86 processors will have new enhancements to facilitate more efficient virtualization. Intel's code names for their virtualization features are "Vanderpool" and "Silvervale"; AMD uses the code name "Pacifica".
x86 and compatibles have been designed, manufactured and sold by a number of companies, including:
- Chips and Technologies
- National Semiconductor
- Rise Technology
- Texas Instruments
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